The present application claims priority from JP 2007-072706 filed on Mar. 20, 2007. The present invention relates to a method of manufacturing an electronic device, and a substrate and a semiconductor device, and more particularly to a method of manufacturing an electronic device having a structure in which a substrate body and a conductive pattern formed thereon through an insulating layer are connected to each other by using a bump, and a substrate and a semiconductor device.
For example, there have been provided various electronic apparatuses in which an electrode and a conductive pattern are formed on a substrate such as a semiconductor substrate or a glass board. As one of them, a semiconductor device referred to as a chip size package has been provided (for example, see Patent Document 1).
The chip size package has a structure in which a rewiring (a wiring for packaging) is formed through a passivation layer (a protecting layer) on a device forming surface of a semiconductor chip obtained by dicing a wafer to be a semiconductor substrate.
In order to manufacture a chip size package disclosed in the Patent Document 1, moreover, a plurality of electrodes is first formed on a semiconductor chip region of a semiconductor wafer and a bump is formed on each of the electrodes.
The bump is formed by a bonding wire using a bonding device. For a specific forming procedure, in the bonding device, a bonding wire extended from a capillary is first bonded to an electrode pad and the capillary is subsequently lifted while the bonding wire is reeled out, and the bonding wire thus reeled out is then cut to form a bump.
For this reason, the bump formed by the bonding wire has a variation in a height from a surface (the electrode pad) on which the bump is formed and it is hard to form a rewiring to be connected to the bump in this state. As a next step, therefore, there is carried out a processing (a leveling processing) for applying a load to each formed bump in a lump to substantially flatten an upper part of the bump.
Subsequently, a semiconductor wafer having the bump formed thereon is covered with a resin, and furthermore, the resin is polished to expose an upper surface of the bump from the resin. Then, a solder ball is formed on each bump exposed from the resin, and thereafter, the semiconductor wafer is subjected to a dividing processing (a dicing processing) every semiconductor chip region so that a chip size package is manufactured.
[Patent Document 1]
JP-A-2002-313985
In a method according to the Patent Document 1, however, it is necessary to carry out the leveling processing for applying a load to each bump in a lump, thereby flattening an upper part of the bump in order to correct a variation in a height of the bump. For this reason, there is a problem in that a manufacturing process is complicated.
In the method according to the Patent Document 1, moreover, an insulating layer is formed to cover the bump. Therefore, there is required a polishing step of polishing the insulating layer to expose the bump. In order to form a rewiring after the polishing step, moreover, a processing (a so-called desmear processing) for roughening a surface of the insulating layer is required when a nonelectrolytic plating method is used, for example. For this reason, a processing for forming a plated layer is complicated. As a result, a manufacturing cost of a semiconductor device is increased.
Moreover, it is also possible to form a conductive layer by a sputtering method or a CVD method. Since the methods require an expensive film forming apparatus having a vacuum treating container, however, the manufacturing cost is increased. For this reason, they are not practical.